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74VHC221A Dual Non-Retriggerable Monostable Multivibrator
April 1994 Revised May 1999
74VHC221A Dual Non-Retriggerable Monostable Multivibrator
General Description
The VHC221A is an advanced high speed CMOS Monostable Multivibrator fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. Each multivibrator features both a negative, A, and a positive, B, transition triggered input, either of which can be used as an inhibit input. Also included is a clear input that when taken LOW resets the one-shot. The VHC221A can be triggered on the positive transition of the clear while A is held LOW and B is held HIGH. The VHC221A is non-retriggerable, and therefore cannot be retriggered until the output pulse times out. The output pulse width is determined by the equation: PW = (Rx)(Cx); where PW is in seconds, R is in ohms, and C is in farads. Limits for Rx and Cx are: External capacitor, Cx: No limit External resistors, Rx: VCC= 2.0V, 5 k min VCC > 3.0V, 1 k min An input protection circuit ensures that 0 to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages.
Features
s High Speed: tPD = 8.1 ns (typ) at VCC = 5V s Low Power Dissipation: ICC = 4 A (Max) at TA = 25C s Active State: ICC = 600 A (Max) at TA = 25C s High Noise Immunity: VNIH = VNIL = 28% VCC (min) s Power down protection is provided on all inputs s Pin and function compatible with 74HC221A
Ordering Code:
Order Number 74VHC221AM 74VHC221ASJ 74VHC221AMTC 74VHC221AN Package Number M16A M16D MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
(c) 1999 Fairchild Semiconductor Corporation
DS011680.prf
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74VHC221A
Truth Table
Inputs Outputs CLR H H H H L
A X L L
H = HIGH Voltage Level L = LOW Voltage Level X: Don't Care
B H L

Q L Q H L H L H
Function Output Enable Inhibit Inhibit Output Enable Output Enable Reset
H
X H X

X

= HIGH-to-LOW Transition = LOW-to-HIGH Transition
Block Diagrams
Note A: Cx, Rx, Dx are external Capacitor, Resistor, and Diode, respectively. Note B: External clamping diode, Dx; External capacitor is charged to VCC level in the wait state, i.e. when no trigger is applied. If the supply voltage is turned off, Cx discharges mainly through the internal (parasitic) diode. If Cx is sufficiently large and VCC drops rapidly, there will be some possibility of damaging the IC through in rush current or latch-up. If the capacitance of the supply voltage filter is large enough and VCC drops slowly, the in rush current is automatically limited and damage to the IC is avoided. The maximum value of forward current through the parasitic diode is mined as follows: tf (VCC -0.7) Cx/20 mA (tf is the time between the supply voltage turn off and the supply voltage reaching 0.4 VCC) In the event a system does not satisfy the above condition, an external clamping diode (Dx) is needed to protect the IC from rush current.
20 mA. In the case of a large Cx, the limit of fall time of the supply voltage is deter-
System Diagram
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74VHC221A
Timing Chart
Functional Description
1. Stand-by State The external capacitor (Cx) is fully charged to VCC in the Stand-by State. That means, before triggering, the QP and QN transistors which are connected to the Rx/ Cx node are in the off state. Two comparators that relate to the timing of the output pulse, and two reference voltage supplies turn off. The total supply current is only leakage current. 2. Trigger Operation Trigger operation is effective in any of the following three cases. First, the condition where the A input is LOW, and B input has a rising signal; second, where the B input is HIGH, and the A input has a falling signal; and third, where the A input is LOW and the B input is HIGH, and the CLR input has a rising signal. After a trigger becomes effective, comparators C1 and C2 start operating, and QN is turned on. The external capacitor discharges through QN. The voltage level at the Rx/Cx node drops. If the Rx/Cx voltage level falls to the internal reference voltage VrefL, the output of C1 becomes LOW. The flip-flop is then reset and QN turns off. At that moment C1 stops but C2 continues operating. After QN turns off, the voltage at the Rx/Cx node starts rising at a rate determined by the time constant of external capacitor Cx and resistor Rx. Upon triggering, output Q becomes HIGH, following some delay time of the internal F/F and gates. It stays HIGH even if the voltage of Rx/Cx changes from falling to rising. When Rx/Cx reaches the internal reference voltage VrefH, the output of C2 becomes LOW, the output Q goes LOW and C2 stops its operation. That means, after triggering, when the voltage level of the Rx/Cx node reaches VrefH, the IC returns to its MONOSTABLE state. With large values of Cx and Rx, and ignoring the discharge time of the capacitor and internal delays of the IC, the width of the output pulse, t W (OUT), is as follows: tW (OUT) = 1.0 Cx Rx 3. Reset Operation In normal operation, the CLR input is held HIGH. If CLR is LOW, a trigger has no affect because the Q output is held LOW and the trigger control F/F is reset. Also, Qp turns on and Cx is charged rapidly to VCC . This means if CLR is set LOW, the IC goes into a wait state.
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74VHC221A
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC ) DC Input Voltage (VIN) DC Output Voltage (VOUT) Input Diode Current (IIK) Output Diode Current (IOK) DC Output Current (IOUT) DC VCC/Current (ICC) Storage Temperature (TSTG) Lead Temperature (TL) Soldering, 10 seconds 260C -0.5V to +7.0V -0.5V to +7.0V -0.5 to VCC +0.5V -20 mA 20 mA 25 mA 50 mA -65C to 150C
Recommended Operating Conditions (Note 2)
Supply Voltage (VCC) Input Voltage (VIN) Output Voltage (VOUT ) Operating Temperature (Topr) Input Rise and Fall Time (tr, tf) (CLR only) VCC = 3.3V 0.3V VCC = 5.0V 0.5V External Capacitor - Cx External Resistor - Rx 0 100 ns/V 0 20 ns/V No Limitation (Note 3) F >5 k (Note 3) (VCC = 2.0V) >1 k (Note 3) (VCC > 3.0V)
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommended operation outside data book specifications. Note 2: Unused inputs must be used HIGH or LOW. They may not float. Note 3: The maximum allowable values of Cx and Rx are a function of the leakage of capacitor Cx, the leakage of the device, and leakage due to board layout and surface resistance. Susceptibility to externally induced noise signals may occur for Rx> 1 M.
2.0V to +5.5V 0V to +5.5V 0V to VCC -40 to +85C
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage VCC (V) 2.0 3.0 - 5.5 2.0 3.0 - 5.5 2.0 3.0 4.5 3.0 4.5 VOL LOW Level Output Voltage 2.0 3.0 4.5 3.0 4.5 IIN IIN ICC ICC Input Leakage Current Rx/Cx Terminal Off-State Current Quiescent Supply Current Active--State (Note 4) Supply Current
Note 4: Per Circuit
TA = 25C Min 1.50 0.7 VCC 0.50 0.3 VCC 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 0.1 0.25 4.0 160 380 560 250 500 750 2.0 3.0 4.5 Typ Max
TA = -40 to 85C Min 1.50 0.7 VCC 0.50 0.3 VCC 1.9 2.9 4.4 2.48 3.80 0.1 0.1 0.1 0.44 0.44 1.0 2.50 40.0 280 650 975 Max
Units V V
Conditions
VIN = VIH IOH = -50 A V or VIL IOH = -4 mA IOH = -8 mA VIN = VIH IOL = 50 A or VIL V IOL = 4 mA IOL = 8 mA A A A A VIN = 5.5V or GND VIN = VCC or GND VIN = VCC or GND VIN = VCC or GND Rx/Cx = 0.5 VCC
V
0 - 5.5 5.5 5.5 3.0 4.5 5.5
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74VHC221A
AC Electrical Characteristics (Note 6)
Symbol tPLH tPHL Parameter Propagation Delay Time (A, B-Q, Q) 5.0 0.5 tPLH tPHL Propagation Delay Time (CLR Trigger--Q, Q) 5.0 0.5 tPLH tPHL Propagation Delay Time (CLR--Q, Q) 5.0 0.5 tWOUT Output Pulse Width 2.0 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 twOUT Output Pulse Width Error Between Circuits (In same Package) CIN CPD Input Capacitance Power Dissipation Capacitance
Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) = CPD*VCC*fIN+ I CC1*Duty/100 + ICC/2 (per Circuit) ICC1: Active Supply Current Duty: % Note 6: Refer to 74VHC221A Timing Chart.
VCC (V) 3.3 0.3
TA = 25C Min Typ 13.4 15.9 8.1 9.6 14.5 17.0 8.7 10.2 10.3 12.8 6.3 7.8 415 345 312 160 133 90 90 0.9 0.9 100 100 1.0 1.0 1 4 73 10 240 200 110 110 1.1 1.1 Max 20.6 24.1 12.0 14.0 22.4 25.9 12.9 14.9 15.8 19.3 9.4 11.4
TA = -40C to +85C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max 24.0 27.5 14.0 16.0 26.0 29.5 15.0 17.0 18.5 22.0 11.0 13.0
Units ns
Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CX = 28 pF CL = 50 pF RX = 6 k CL = 50 pF Cx = 28 pF Rx = 2 k CL = 50 pF Cx = 0.01 F Rx = 10 k CL = 50 pF Cx = 0.1 F Rx = 10 k
ns ns ns ns ns
3.3 0.3
3.3 0.3
ns 300 240 90 90 0.9 0.9 110 110 1.1 1.1
ns s ms
% 10 pF pF VCC = Open (Note 5)
AC Operating Requirement
Symbol tW(L) tW(H) tW(L) Parameter Minimum Trigger Pulse Width Minimum Clear Pulse Width VCC (V) 3.3 5.0 3.3 5.0 TA = 25C Min 5.0 5.0 5.0 5.0 Typ Max TA = -40C to +85C Min 5.0 5.0 5.0 5.0 Max Units ns ns
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74VHC221A
Device Characteristics
twout*Cx Characteristics (typ)
Output Pulse Width Constant K-Supply Voltage (Typical)
Input Equivalent Circuit
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74VHC221A
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D
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74VHC221A
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16
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74VHC221A Dual Non-Retriggerable Monostable Multivibrator
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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